Looks like we've taken the FSB as far as we could go and still run rock stable at 400 MHz. Now, let's examined the memory. We've managed to get our hands on some DDR2-1066 modules - Kingston's KHX-8500 2 GB kit. Swapping them in, we ran the same tests under two settings - synchronous with tighter timings (4-4-4-9) and asynchronous with SPD timings at DDR2-1000 (running the memory asynchronously at 4:5). Here is the SPD data from these modules:
For your information, Kingston officially states these memory moduls are PC8500 memory modules at 2.2 volts. Remember, we're running them throughout these tests at 1.9 volts.
Here are the results:
| Sync | Async | |
| 400 Mhz 4-4-4-9 | 400 Mhz 5-7-7-20 | |
| Bandwidth | 6450.78 MB/s | 6719.65 MB/s |
| Latency | ||
| 4 byte stride | 3 cycles | 3 cycles |
| 16 byte stride | 8 | 8 |
| 64 byte stride | 34 | 31 |
| 256 byte stride | 120 | 110 |
| 512 byte stride | 137 | 127 |
| Compared to 400 MHz 4-4-4-9 | ||
| Bandwidth | 4.17% | |
| Latency | ||
| 4 byte stride | 0 cycles | |
| 16 byte stride | 0 | |
| 64 byte stride | -3 | |
| 256 byte stride | -10 | |
| 512 byte stride | -10 |
Next, the SuperPi results under both settings.
| Sync | Async | |
| 400 Mhz 4-4-4-9 | 400 Mhz 5-7-7-20 | |
| Iterations | seconds | seconds |
| 1 | 11 | 11 |
| 2 | 21 | 21 |
| 3 | 31 | 31 |
| 4 | 42 | 42 |
| 5 | 52 | 52 |
| 6 | 62 | 62 |
| 7 | 72 | 72 |
| 8 | 82 | 82 |
| 9 | 92 | 92 |
| 10 | 102 | 102 |
| 11 | 112 | 112 |
| 12 | 122 | 122 |
| 13 | 132 | 132 |
| 14 | 142 | 142 |
| 15 | 152 | 152 |
| 16 | 162 | 162 |
| 17 | 172 | 172 |
| 18 | 182 | 182 |
| 19 | 192 | 192 |
| 20 | 202 | 202 |
| 21 | 212 | 212 |
| 22 | 220 | 220 |
Now, this is particularly interesting - very interesting indeed. From Sciencemark Membench's results we can see bandwidth wise, asynchronous results at 400 MHz FSB with 1000 MHz memory offer an advantage in both bandwidth and latency compared to running synchronous at 400 MHz with tighter timings. However, those two advantages didn't translate to real world increase in performance - the overall SuperPi 8M test results on both settings, hell, even the time taken with each iterations are the same. Now compare these SuperPi results with our previous 400 and 466 MHz results, taken with much more 'relaxed' timings - '5-5-5-18'. The difference: 6 seconds faster from 400 MHz and 2 seconds slower than 466 MHz. These are so small you will not notice them in real life.
Confused yet? What does it all mean? What's the point of these tests?
If you're lucky enough to get a more overclockable processor or employ a much more effective cooling solution, the performance bottleneck at very high FSBs on a Core 2 Duo platform is not on the DDR2 modules or the processor itself but rather on the chipset or more precisely, the memory controller. The Intel P965 chipset was designed for synchronous settings in mind and it looks like the ceiling for this chipset was set to 400 MHz. It make do with asynchronous modes by lowering latencies (no doubt to offset the high latencies of higher clocked memory modules). At least that's what we think.
Why?
We saw a trend with synchronous mode that with every 66 MHz jump from 266 MHz to 400 MHz, overall latency increases. We did not see a similar situation between 400 and 466 MHz. At 400 MHz, internal chipset latencies are already being stretch to the limit. At higher clocks it simply can not use anymore 'looser' internal timings to compensate and transfer data from the memory to the processor fast enough - limiting us from gaining any increase in performance. Look closely at bandwidth numbers from 466 MHz FSB and 400 MHz with DDR2-1000 modules test results to see what we mean - they are practically similar. The reason we're seeing higher performance from the higher clocked FSB is because 'real' latency or the actual time spent on idle cycles went down with higher clocks.
Latencies in terms of cycles stayed constant, but the chipset / memory controller is running at a higher clock. Thus latencies in time spent (ns) are lower - more data went through..
However, since the chipset is not able to loosen its internal timings any more past 400 MHz, it's only a matter of time before we hit a MHz brick wall should we continue to increase the FSB. It's obvious why some overclockers reported a decrease in performance with FSB higher than 400 MHz - the chipset's internal latency was more likely 'loosened' (either by Intel or motherboard manufacturers) at higher clocks - a much needed compromise to allow stability above 400 MHz.
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